Multi-BCON development/evaluation board

Based on DCT Arria 10 SoM SoC development board, 6 Basler BCON cameras were hooked up via BCON LVDS. The current implementation displays all 6 cameras at the same time on the screen. Each camera can be configured individually running Pylon on the HPS subsystem.

Technical Overview:

The 6 Basler BCON cameras are connected to the Arria 10 FPGA via the FMC connector by the BCON LVDS interface. The BCON receiver module has been designed for proper data receiving. It's output video stream format is similar to "clocked video" (Intel ViP Suite terminology). This stream is converted to Avalon-stream interface by CVI (Clocked video input) module from ViP suite.

Only cores from Intel ViP Suite are used for panorama image creation. The same structure is used for providing full-scale image from one selected camera. This mode is fully software-defined. All modules that require software control are connected to internal Avalon bus with the Arria 10 HPS as a master.

Image stream has two possible paths: Linux and Direct modes.

FPGA structure

                                                                                                   1: FPGA structure

The system includes a Sync-Generator module that provides a synchronization signal for all cameras to acquire the images at the same time.

 

For debugging purposes the Test Pattern Generator from Intel ViP suite was included in each channel processing sub-module. So each camera can be independently substituted by test patterns.

The Scaler from Intel ViP suite allows scaling the input image to any required size. It's used to scale down the images to 640x480 pixel resolution for panorama mode and to scale any input image to final 1920x1080/1920x1200 resolution for single camera mode.

For further technical information, please contact heiko.henkel@dreamchip.de

Title Description Format
Schematics 6x BCON FMC connector PDF
Schematics Schematic fix txt

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